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HT49R50A-1/HT49C50-1/HT49C50L LCD Type 8-Bit MCU
Technical Document
* Tools Information * FAQs * Application Note - HA0017E Controlling the Read/Write Function of the HT24 Series EEPROM Using the HT49 Series MCUs - HA0024E Using the RTC in the HT49 MCU Series - HA0025E Using the Time Base in the HT49 MCU Series - HA0026E Using the I/O Ports on the HT49 MCU Series - HA0027E Using the Timer/Event Counter in the HT49 MCU Series
Features
* Operating voltage: * On-chip crystal, RC and 32768Hz crystal oscillator * HALT function and wake-up feature reduce power
fSYS=4MHz: 2.2V~5.5V for HT49R50A-1/HT49C50-1 fSYS=8MHz: 3.3V~5.5V for HT49R50A-1/HT49C50-1 fSYS=500kHz: 1.2V~2.2V for HT49C50L
* 8 input lines * 12 bidirectional I/O lines * Two external interrupt input * Two 8-bit programmable timer/event counter with
consumption
* 6-level subroutine nesting * Bit manipulation instruction * 15-bit table read instruction * Up to 0.5ms instruction cycle with 8MHz system clock
PFD (programmable frequency divider) function
* LCD driver with 332, 333 or 324 segments * 4K15 program memory * 1608 data memory RAM * Real Time Clock (RTC) * 8-bit prescaler for RTC * Watchdog Timer * Buzzer output
for HT49R50A-1/HT49C50-1
* Up to 8ms instruction cycle with 500kHz system clock
for HT49C50L
* 63 powerful instructions * All instructions in 1 or 2 machine cycles * Low voltage reset/detector function
for HT49R50A-1/HT49C50-1
* 48-pin SSOP, 100-pin QFP package
General Description
The HT49R50A-1/HT49C50-1/HT49C50L are 8-bit, high performance, RISC architecture microcontroller devices specifically designed for a wide range of LCD applications. The mask version HT49C50-1 and HT49C50L are fully pin and functionally compatible with the OTP version HT49R50A-1 device. The HT49C50L is a low voltage version, with the ability to operate at a minimum power supply of 1.2V, making it suitable for single cell battery applications. The advantages of low power consumption, I/O flexibility, programmable frequency divider, timer functions, oscillator options, HALT and wake-up functions and buzzer driver in addition to a flexible and configurable LCD interface, enhance the versatility of these devices to control a wide range of LCD-based application possibilities such as measuring scales, electronic multimeters, gas meters, timers, calculators, remote controllers and many other LCD-based industrial and home appliance applications.
Rev. 2.10
1
April 24, 2006
HT49R50A-1/HT49C50-1/HT49C50L
Block Diagram
In te rru p t C ir c u it P ro g ra m m e m o ry P ro g ra m C o u n te r STACK IN T C fT M U X fS
TM R0C TM R0 PFD0 TM R1C TM R1 PFD1 M
RTC O ut P B 2 /T M R 0 P B 3 /T M R 1 TM R 0O V
1D YS
U X
In s tr u c tio n R e g is te r
fS Y S T im e B a s e O u t fT 1 D
MP
M U
X
DATA M e m o ry RTC W DT M U X S Y S C L K /4 OSC3 OSC4
RTC
OSC
In s tr u c tio n D ecoder ALU T im in g G e n e r a tio n
MUX
T im e B a s e STATUS PC PORT B BP PB
W DT OSC
S h ifte r
PC 0~PC3
P B 0 /IN T 0 P B 1 /IN T 1 P B 2 /T M R 0 P B 3 /T M R 1 PB4~PB7
OSC2 OSC4
OS RE VD VS OS S
S D
C1
ACC LCD M e m o ry L C D D r iv e r
C3
PORT A PA
PA PA PA PA PA
0 /B Z 1 /B Z 2 3 /P F D 4~PA7
C O M 0~ COM2
C O M 3/ SEG 32
SEG 0~ SEG 31
H ALT
E N /D IS
L V D /L V R
Rev. 2.10
2
April 24, 2006
HT49R50A-1/HT49C50-1/HT49C50L
Pin Assignment
SEG N N N N N N N N OSC OSC VD OSC OSC RE P A 0 /B P A 1 /B PA P A 3 /P F PA D D C C C C C C C C S Z Z 1 2 3 4 0
1 5 C C C C C 6 7 T0 T1 R0 P P P P P P P P R1 B4 B5 B6 B7 C0 C1 C2 C3 NC NC NC NC NC NC NC NC NC SS 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 4445 46 4748 49 50 8 7 6 5 4 3 2
100 99 98 97 96 9594 93 92 91 90 89 88 87 86 8584 83 82 81
4 2
P A 0 /B Z 1 2 3 4 5 6 7 8 9 P A 1 /B Z PA2 P A 3 /P F D PA4 PA5 PA6 PA7 P B 0 /IN T 0 P B 1 /IN T 1 P B 2 /T M R 0 P B 3 /T M R 1 PB4 PB5 VSS VLCD V1 V2 C1 C2 COM0 COM1 COM2 C O M 3 /S E G 3 2
48 47 46 45 44 43 42 41 40 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
RES OSC1 OSC2 VDD OSC3 OSC4 SEG 10 SEG 11 SEG 12 SEG 13 SEG 14 SEG 15 SEG 16 SEG 17 SEG 18 SEG 19 SEG 20 SEG 21 SEG 22 SEG 23 SEG 24 SEG 25 SEG 26 SEG 27
V P B 0 /IN P B 1 /IN P B 2 /T M P B 3 /T M
PA N N N N N PA PA
80 79 78 77 76 75 74 73 72 71 70 69 68
H T 4 9 R 5 0 A -1 /H T 4 9 C 5 0 -1 /H T 4 9 C 5 0 L 1 0 0 Q F P -A
67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
SEG1 SEG2 SEG3 NC NC NC SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG1 SEG1 SEG1 SEG1 SEG1 SEG1 SEG1 SEG1 SEG1 SEG1 SEG2 SEG2 NC NC NC NC NC NC 1
0 1 2 3 4 5 6 7 8 9 0
NC SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG COM COM COM COM C2 C1 V2 V1 VLC D 22 23 24 25 26 27 28 29 30 31 3 /S E G 3 2 0 1 2
H T 4 9 R 5 0 A -1 /H T 4 9 C 5 0 -1 /H T 4 9 C 5 0 L 4 8 S S O P -A
Rev. 2.10
3
April 24, 2006
HT49R50A-1/HT49C50-1/HT49C50L
Pin Description
Pin Name PA0/BZ PA1/BZ PA2 PA3/PFD PA4~PA7 PB0/INT0 PB1/INT1 PB2/TMR0 PB3/TMR1 PB4~PB7 PC0~PC3 I/O Options Description PA0~PA7 constitute an 8-bit bidirectional input/output port with Schmitt trigger input capability. Each pin on port can be configured as wake-up input by options. PA0~PA3 can be configured as CMOS output or NMOS input/outWake-up I/O Pull-high or None put with or without pull-high resistor by options. PA4~PA7 are always CMOS or NMOS pull-high NMOS input/output. Of the eight bits, PA0~PA1 can be set as I/O pins or buzzer outputs by options. PA3 can be set as an I/O pin or as a PFD output also by options. PB0~PB7 constitute an 8-bit Schmitt trigger input port. Each pin on port are with pull-high resistor. Of the eight bits, PB0 and PB1 can be set as input pins or as external interrupt control pins (INT0) and (INT1) respectively, by software application. PB2 and PB3 can be set as input pin or as timer/event counter input pin TMR0 and TMR1 also by software application.
I
3/4
I/O
PC0~PC3 constitute a 4-bit bidirectional input/output port with Schmitt trigPull-high or None ger input capability. On the port, such can be configured as CMOS output or CMOS or NMOS NMOS input/output with or without pull-high resistor by options. 3/4 3/4 3/4 1/2, 1/3 or 1/4 Duty 3/4 Voltage pump for HT49R50A-1/HT49C50-1. LCD power supply for HT49C50L. LCD power supply for HT49R50A-1/HT49C50-1. Voltage pump for HT49C50L. Voltage pump SEG32 can be set as a segment or as a common output driver for LCD panel by options. COM0~COM2 are outputs for LCD panel plate. LCD driver outputs for LCD panel segments OSC1 and OSC2 are connected to an RC network or a crystal (by options) for the internal system clock. In the case of RC operation, OSC2 is the output terminal for 1/4 system clock. The system clock may come from the RTC oscillator. If the system clock comes from RTCOSC, these two pins can be floating. Real time clock oscillators. OSC3 and OSC4 are connected to a 32768Hz crystal oscillator for timing purposes or to a system clock source (depending on the options). No built-in capacitor Schmitt trigger reset input, active low. Negative power supply, ground Positive power supply
V2 VLCD V1, C1, C2 COM0~COM2 COM3/SEG32 SEG0~SEG31
I I I O O
OSC1 OSC2
I O
Crystal or RC
OSC3 OSC4 RES VSS VDD
I O I 3/4 3/4
RTC or System Clock 3/4 3/4 3/4
Absolute Maximum Ratings
Supply Voltage..........................VSS-0.3V to VSS+6.0V* Storage Temperature ............................-50C to 125C Operating Temperature ...........................-40C to 85C Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. * For HT49R50A-1/HT49C50-1 ** For HT49C50L Supply Voltage ........................VSS-0.3V to VSS+2.5V** Input Voltage..............................VSS-0.3V to VDD+0.3V
Rev. 2.10
4
April 24, 2006
HT49R50A-1/HT49C50-1/HT49C50L
D.C. Characteristics
VDD=1.5V for HT49C50L, VDD=3V & VDD=5V for HT49R50A-1 and HT49C50-1 Test Conditions Symbol Parameter VDD Conditions For HT49C50L VDD Operating Voltage 3/4 LVR disable, fSYS=4MHz (for HT49R50A-1/HT49C50-1) fSYS=8MHz (for HT49R50A-1/HT49C50-1) VLCD LCD Power Supply (Note *) 3/4 For HT49R50A-1/HT49C50-1, VA5.5V 1.2 2.2 3.3 2.2 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 No load 3/4 3/4 3/4 No load, system HALT, LCD off at HALT 3/4 3/4 3/4 No load, system HALT, LCD On at HALT, C type 3/4 3/4 3/4 No load, system HALT LCD On at HALT, C type 3/4 3/4 No load, system HALT, LCD on at HALT, R type, 1/2 bias No load, system HALT, LCD on at HALT, R type, 1/3 bias No load, system HALT, LCD on at HALT, R type, 1/2 bias No load, system HALT, LCD on at HALT, R type, 1/3 bias 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 0 3/4 3/4 3/4 3/4 60 1 3 50 1 3 4 2.5 0.3 0.6 0.1 3/4 3/4 1 2.5 10 0.5 2 6 17 34 13 26 14 28 10 20 3/4 2.2 5.5 5.5 5.5 100 2 5 100 2 5 8 5 0.6 1 0.5 1 2 2 5 20 1 5 10 30 60 25 50 25 50 20 40 0.3VDD V V V V mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA V Min. Typ. Max. Unit Ta=25C
1.5V No load, fSYS=455kHz IDD1 Operating Current (Crystal OSC) 3V 5V 1.5V No load, fSYS=400kHz IDD2 Operating Current (RC OSC) Operating Current (Crystal OSC, RC OSC) Operating Current (fSYS=RTC OSC) 3V 5V IDD3 5V 1.5V IDD4 3V 5V 1.5V ISTB1 Standby Current (*fS=T1) 3V 5V 1.5V ISTB2 Standby Current (*fS=RTC OSC) 3V 5V 1.5V ISTB3 Standby Current (*fS=WDT RC OSC) 3V 5V ISTB4 Standby Current (*fS=RTC OSC) Standby Current (*fS=RTC OSC) Standby Current (*fS=WDT RC OSC) Standby Current (*fS=WDT RC OSC) Input Low Voltage for I/O Ports, TMR and INT 3V 5V 3V 5V 3V 5V 3V 5V 3/4 No load, fSYS=8MHz No load, fSYS=4MHz No load, fSYS=4MHz
ISTB5
ISTB6
ISTB7
VIL1
Rev. 2.10
5
April 24, 2006
HT49R50A-1/HT49C50-1/HT49C50L
Test Conditions Symbol Parameter VDD VIH1 VIL2 VIH2 Input High Voltage for I/O Ports, TMR and INT Input Low Voltage (RES) Input High Voltage (RES) 3/4 3/4 3/4 1.5V IOL1 I/O Port Sink Current 3V 5V 1.5V IOH1 I/O Port Source Current 3V 5V IOL2 LCD Common and Segment Current LCD Common and Segment Current 3V 5V 3V 5V 1.5V RPH Pull-high Resistance 3V 5V VLVR VLVD Note: Low Voltage Reset Voltage Low Voltage Detector Voltage 3/4 3/4 3/4 3/4 3/4 VOH=0.9VDD VOL=0.1VDD VOH=0.9VDD VOL=0.1VDD Conditions For HT49C50L For HT49R50A-1/HT49C50-1 3/4 3/4 0.8VDD 0.7VDD 0 0.9VDD 0.4 6 10 -0.3 -2 -5 210 350 -80 -180 75 20 10 2.7 3.0 3/4 3/4 3/4 3/4 0.8 12 25 -0.6 -4 -8 420 700 -160 -360 150 60 30 3.2 3.3 VDD VDD 0.4VDD VDD 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 300 100 50 3.6 3.6 V V V V mA mA mA mA mA mA mA mA mA mA kW kW kW V V Min. Typ. Max. Unit
IOH2
* for the value of VA refer to the LCD driver section. *fS please refer to WDT clock option
Rev. 2.10
6
April 24, 2006
HT49R50A-1/HT49C50-1/HT49C50L
A.C. Characteristics
VDD=1.5V for HT49C50L, VDD=3V & VDD=5V for HT49R50A-1 and HT49C50-1 Test Conditions Symbol Parameter VDD 3/4 fSYS1 System Clock (Crystal OSC) 3/4 3/4 3/4 fSYS2 System Clock (RC OSC) System Clock (32768Hz Crystal OSC) RTC Frequency 3/4 3/4 fSYS3 fRTCOSC 3/4 3/4 3/4 fTIMER Timer I/P Frequency 3/4 3/4 1.5V tWDTOSC Watchdog Oscillator Period 3V 5V tRES tSST tLVR tINT External Reset Low Pulse Width System Start-up Timer Period Low Voltage Width to Reset Interrupt Pulse Width 3/4 3/4 3/4 3/4 For HT49C50L For HT49R50A-1/HT49C50-1 Wake-up from HALT 3/4 For HT49C50L For HT49R50A-1/HT49C50-1 3/4 Conditions 1.2V~2.2V (for HT49C50L) 2.2V~5.5V 3.3V~5.5V 1.2V~2.2V (for HT49C50L) 2.2V~5.5V 3.3V~5.5V 3/4 3/4 1.2V~2.2V (for HT49C50L) 2.2V~5.5V 3.3V~5.5V 400 400 400 400 400 400 3/4 3/4 0 0 0 35 45 32 10 1 3/4 0.25 10 1 3/4 3/4 3/4 3/4 3/4 3/4 32768 32768 3/4 3/4 3/4 70 90 65 3/4 3/4 1024 1 3/4 3/4 500 4000 8000 500 4000 8000 3/4 3/4 500 4000 8000 140 180 130 3/4 3/4 3/4 2 3/4 3/4 kHz kHz kHz kHz kHz kHz Hz Hz kHz kHz kHz ms ms ms ms ms *tSYS ms ms ms Min. Typ. Max. Unit Ta=25C
Note:
*tSYS= 1/fSYS1, 1/fSYS2 or 1/fSYS3
Rev. 2.10
7
April 24, 2006
HT49R50A-1/HT49C50-1/HT49C50L
Functional Description
Execution Flow The system clock is derived from either a crystal or an RC oscillator or a 32768Hz crystal oscillator. It is internally divided into four non-overlapping clocks. One instruction cycle consists of four system clock cycles. Instruction fetching and execution are pipelined in such a way that a fetch takes one instruction cycle while decoding and execution takes the next instruction cycle. The pipelining scheme causes each instruction to effectively execute in a cycle. If an instruction changes the value of the program counter, two cycles are required to complete the instruction. Program Counter - PC The program counter (PC) is of 12 bits wide and controls the sequence in which the instructions stored in the program ROM are executed. The contents of the PC can specify a maximum of 4096 addresses.
S y s te m O S C 2 (R C C lo c k o n ly ) PC PC F e tc h IN S T (P C ) E x e c u te IN S T (P C -1 ) PC+1 PC+2 T1 T2 T3 T4 T1
After accessing a program memory word to fetch an instruction code, the value of the PC is incremented by one. The PC then points to the memory word containing the next instruction code. When executing a jump instruction, conditional skip execution, loading a PCL register, a subroutine call, an initial reset, an internal interrupt, an external interrupt, or returning from a subroutine, the PC manipulates the program transfer by loading the address corresponding to each instruction. The conditional skip is activated by instructions. Once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get a proper instruction; otherwise proceed with the next instruction. The lower byte of the PC (PCL) is a readable and writeable register (06H). Moving data into the PCL performs a short jump. The destination is within 256 locations.
T2 T3 T4 T1 T2 T3 T4
F e tc h IN S T (P C + 1 ) E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 ) E x e c u te IN S T (P C + 1 )
Execution Flow Program Counter Mode *11 Initial Reset External Interrupt 0 External Interrupt 1 Timer/Event Counter 0 overflow Timer/Event Counter 1 overflow Time Base Interrupt RTC Interrupt Skip Loading PCL Jump, Call Branch Return From Subroutine *11 #11 S11 *10 #10 S10 *9 #9 S9 *8 #8 S8 0 0 0 0 0 0 0 *10 0 0 0 0 0 0 0 *9 0 0 0 0 0 0 0 *8 0 0 0 0 0 0 0 *7 0 0 0 0 0 0 0 *6 0 0 0 0 0 0 0 *5 0 0 0 0 0 0 0 *4 0 0 0 0 1 1 1 *3 0 0 1 1 0 0 1 *2 0 1 0 1 0 1 0 *1 0 0 0 0 0 0 0 *0 0 0 0 0 0 0 0
Program Counter + 2 @7 #7 S7 @6 #6 S6 @5 #5 S5 @4 #4 S4 @3 #3 S3 @2 #2 S2 @1 #1 S1 @0 #0 S0
Program Counter Note: *11~*0: Program counter bits #11~#0: Instruction code bits 8 S11~S0: Stack register bits @7~@0: PCL bits April 24, 2006
Rev. 2.10
HT49R50A-1/HT49C50-1/HT49C50L
When a control transfer takes place, an additional dummy cycle is required. Program Memory - ROM The program memory (ROM) is used to store the program instructions which are to be executed. It also contains data, table, and interrupt entries, and is organized into 4096 15 bits which are addressed by the program counter and table pointer. Certain locations in the ROM are reserved for special usage:
* Location 000H
n00H nFFH 000H 004H 008H 00C H 010H 014H 018H D e v ic e in itia liz a tio n p r o g r a m E x te r n a l in te r r u p t 0 s u b r o u tin e E x te r n a l in te r r u p t 1 s u b r o u tin e T im e r /e v e n t c o u n te r 0 in te r r u p t s u b r o u tin e T im e r /e v e n t c o u n te r 1 in te r r u p t s u b r o u tin e T im e B a s e In te r r u p t R T C In te rru p t P ro g ra m ROM
Location 000H is reserved for program initialization. After chip reset, the program always begins execution at this location.
* Location 004H
L o o k - u p ta b le ( 2 5 6 w o r d s )
F00H FFFH
L o o k - u p ta b le ( 2 5 6 w o r d s ) 1 5 b its N o te : n ra n g e s fro m 0 to F
Location 004H is reserved for the external interrupt service program. If the INT0 input pin is activated, and the interrupt is enabled, and the stack is not full, the program begins execution at location 004H.
* Location 008H
Program Memory
Location 008H is reserved for the external interrupt service program also. If the INT1 input pin is activated, and the interrupt is enabled, and the stack is not full, the program begins execution at location 008H.
* Location 00CH
* Location 018H
Location 018H is reserved for the real time clock interrupt service program. If a real time clock interrupt occurs, and the interrupt is enabled, and the stack is not full, the program begins execution at location 018H.
* Table location
Location 00CH is reserved for the Timer/Event Counter 0 interrupt service program. If a timer interrupt results from a Timer/Event Counter 0 overflow, and if the interrupt is enabled and the stack is not full, the program begins execution at location 00CH.
* Location 010H
Location 010H is reserved for the Timer/Event Counter 1 interrupt service program. If a timer interrupt results from a Timer/Event Counter 1 overflow, and if the interrupt is enabled and the stack is not full, the program begins execution at location 010H.
* Location 014H
Location 014H is reserved for the Time Base interrupt service program. If a Time Base interrupt occurs, and the interrupt is enabled, and the stack is not full, the program begins execution at location 014H.
Any location in the ROM can be used as a look-up table. The instructions TABRDC [m] (the current page, 1 page=256 words) and TABRDL [m] (the last page) transfer the contents of the lower-order byte to the specified data memory, and the contents of the higher-order byte to TBLH (Table Higher-order byte register) (08H). Only the destination of the lower-order byte in the table is well-defined; the other bits of the table word are all transferred to the lower portion of TBLH, and the remaining 1 bit is read as 0. The TBLH is read only, and the table pointer (TBLP) is a read/write register (07H), indicating the table location. Before accessing the table, the location should be placed in TBLP. All the table related instructions require 2 cycles to complete the operation. These areas may function as a normal ROM depending upon the users requirements.
Table Location Instruction(s) *11 TABRDC [m] TABRDL [m] P11 1 *10 P10 1 *9 P9 1 *8 P8 1 *7 @7 @7 *6 @6 @6 *5 @5 @5 *4 @4 @4 *3 @3 @3 *2 @2 @2 *1 @1 @1 *0 @0 @0
Table Location Note: *11~*0: Table location bits @7~@0: Table pointer bits P11~P8: Current program Counter bits
Rev. 2.10
9
April 24, 2006
HT49R50A-1/HT49C50-1/HT49C50L
Stack Register - STACK The stack register is a special part of the memory used to save the contents of the program counter. The stack is organized into 6 levels and is neither part of the data nor part of the program, and is neither readable nor writeable. Its activated level is indexed by a stack pointer (SP) and is neither readable nor writeable. At a commencement of a subroutine call or an interrupt acknowledgment, the contents of the program counter is pushed onto the stack. At the end of the subroutine or interrupt routine, signaled by a return instruction (RET or RETI), the contents of the program counter is restored to its previous value from the stack. After chip reset, the SP will point to the top of the stack. If the stack is full and a non-masked interrupt takes place, the interrupt request flag is recorded but the acknowledgment is still inhibited. Once the SP is decremented (by RET or RETI), the interrupt is serviced. This feature prevents stack overflow, allowing the programmer to use the structure easily. Likewise, if the stack is full, and a CALL is subsequently executed, a stack overflow occurs and the first entry is lost (only the most recent six return addresses are stored). Data Memory - RAM The data memory (RAM) is designed with 1928 bits, and is divided into two functional groups, namely special function registers and general purpose data memory, most of which are readable/writeable, although some are read only. Of the two types of functional groups, the special function registers consist of an Indirect addressing register 0 (00H), a Memory pointer register 0 (MP0;01H), an Indirect addressing register 1 (02H), a Memory pointer register 1 (MP1;03H), a Bank pointer (BP;04H), an Accumulator (ACC;05H), a Program counter lower-order byte register (PCL;06H), a Table pointer (TBLP;07H), a Table higher-order byte register (TBLH;08H), a Real time clock control register (RTCC;09H), a Status register (STATUS;0AH), an Interrupt control register 0 (INTC0;0BH), a Timer/Event Counter 0 (TMR0;0DH), a Timer/Event Counter 0 control register (TMR0C;0EH), a Timer/Event Counter 1 (TMR1;10H), a Timer/Event Counter 1 control register (TMR1C;11H), I/O registers (PA;12H, PB;14H, PC;16H), and Interrupt control register 1 (INTC1;1EH). On the other hand, the general purpose data memory, addressed from 60H to FFH, is used for data and control information under instruction commands. The areas in the RAM can directly handle arithmetic, logic, increment, decrement, and rotate operations. Except some dedicated bits, Each pin in the RAM can be set and reset by SET [m].i and CLR [m].i. They are also indirectly accessible through the Memory pointer register 0 (MP0;01H) or the Memory pointer register 1 (MP1;03H). Rev. 2.10 10
00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 5FH 60H G e n e ra l P u rp o s e D a ta M e m o ry (1 6 0 B y te s ) FFH IN T C 1 :U nused. R e a d a s 0 0 PC PB TM R1 TM R1C PA TM R0 TM R0C In d ir e c t A d d r e s s in g R e g is te r 0 MP0 In d ir e c t A d d r e s s in g R e g is te r 1 MP1 BP ACC PCL TBLP TBLH RTCC STATUS IN T C 0 S p e c ia l P u r p o s e D a ta M e m o ry
RAM Mapping Indirect Addressing Register Location 00H and 02H are indirect addressing registers that are not physically implemented. Any read/write operation of [00H] and [02H] accesses the RAM pointed to by MP0 (01H) and MP1(03H) respectively. Reading location 00H or 02H indirectly returns the result 00H. While, writing it indirectly leads to no operation. The function of data movement between two indirect addressing registers is not supported. The memory pointer registers, MP0 and MP1, are both 8-bit registers used to access the RAM by combining corresponding indirect addressing registers. MP0 can only be applied to data memory, while MP1 can be applied to data memory and LCD display memory.
April 24, 2006
HT49R50A-1/HT49C50-1/HT49C50L
Accumulator - ACC The accumulator (ACC) is related to the ALU operations. It is also mapped to location 05H of the RAM and is capable of operating with immediate data. The data movement between two data memory locations must pass through the ACC. Arithmetic and Logic Unit - ALU This circuit performs 8-bit arithmetic and logic operations and provides the following functions:
* Arithmetic operations (ADD, ADC, SUB, SBC, DAA) * Logic operations (AND, OR, XOR, CPL) * Rotation (RL, RR, RLC, RRC) * Increment and Decrement (INC, DEC) * Branch decision (SZ, SNZ, SIZ, SDZ etc.)
On entering the interrupt sequence or executing the subroutine call, the status register will not be automatically pushed onto the stack. If the contents of the status is important, and if the subroutine is likely to corrupt the status register, the programmer should take precautions and save it properly. Interrupts The devices provides two external interrupts, two internal timer/event counter interrupts, an internal time base interrupt, and an internal real time clock interrupt. The interrupt control register 0 (INTC0;0BH) and interrupt control register 1 (INTC1;1EH) both contain the interrupt control bits that are used to set the enable/disable status and interrupt request flags. Once an interrupt subroutine is serviced, other interrupts are all blocked (by clearing the EMI bit). This scheme may prevent any further interrupt nesting. Other interrupt requests may take place during this interval, but only the interrupt request flag will be recorded. If a certain interrupt requires servicing within the service routine, the EMI bit and the corresponding bit of the INTC0 or of INTC1 may be set in order to allow interrupt nesting. Once the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the SP is decremented. If immediate service is desired, the stack should be prevented from becoming full. All these interrupts can support a wake-up function. As an interrupt is serviced, a control transfer occurs by pushing the contents of the program counter onto the stack followed by a branch to a subroutine at the specified location in the ROM. Only the contents of the program counter is pushed onto the stack. If the contents of the register or of the status register (STATUS) is altered by the interrupt service program which corrupts the desired control sequence, the contents should be saved in advance. Function
The ALU not only saves the results of a data operation but also changes the status register. Status Register - STATUS The status register (0AH) is of 8 bits wide and contains, a carry flag (C), an auxiliary carry flag (AC), a zero flag (Z), an overflow flag (OV), a power down flag (PDF), and a watchdog time-out flag (TO). It also records the status information and controls the operation sequence. Except the TO and PDF flags, bits in the status register can be altered by instructions similar to other registers. Data written into the status register does not alter the TO or PDF flags. Operations related to the status register, however, may yield different results from those intended. The TO and PDF flags can only be changed by a Watchdog Timer overflow, chip power-up, or clearing the Watchdog Timer and executing the HALT instruction. The Z, OV, AC, and C flags reflect the status of the latest operations.
Bit No. 0
Label C
C is set if the operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction. AC is set if the operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared. Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared. OV is set if the operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared. PDF is cleared by either a system power-up or executing the CLR WDT instruction. PDF is set by executing the HALT instruction. TO is cleared by a system power-up or executing the CLR WDT or HALT instruction. TO is set by a WDT time-out. Unused bit, read as 0 Status (0AH) Register
1 2 3 4 5 6, 7
AC Z OV PDF TO 3/4
Rev. 2.10
11
April 24, 2006
HT49R50A-1/HT49C50-1/HT49C50L
External interrupts are triggered by a high to low transition of INT0 or INT1, and the related interrupt request flag (EIF0;bit 4 of INTC0, EIF1;bit 5 of INTC0) is set as well. After the interrupt is enabled, the stack is not full, and the external interrupt is active, a subroutine call to location 04H or 08H occurs. The interrupt request flag (EIF0 or EIF1) and EMI bits are all cleared to disable other interrupts. The internal Timer/Event Counter 0 interrupt is initialized by setting the Timer/Event Counter 0 interrupt request flag (T0F;bit 6 of INTC0), which is normally caused by a timer overflow. After the interrupt is enabled, and the stack is not full, and the T0F bit is set, a subroutine call to location 0CH occurs. The related interrupt request flag (T0F) is reset, and the EMI bit is cleared to disable further interrupts. The Timer/Event Counter 1 is operated in the same manner but its related interrupt request flag is T1F (bit 4 of INTC1) and its subroutine call location is 10H. The time base interrupt is initialized by setting the time base interrupt request flag (TBF;bit 5 of INTC1), that is caused by a regular time base signal. After the interrupt is enabled, and the stack is not full, and the TBF bit is set, a subroutine call to location 14H occurs. The related interrupt request flag (TBF) is reset and the EMI bit is cleared to disable further interrupts. The real time clock interrupt is initialized by setting the real time clock interrupt request flag (RTF; bit 6 of INTC1), that is caused by a regular real time clock signal. After the interrupt is enabled, and the stack is not full, and the RTF bit is set, a subroutine call to location 18H occurs. The related interrupt request flag (RTF) is reset and the EMI bit is cleared to disable further interrupts. During the execution of an interrupt subroutine, other interrupt acknowledgments are all held until the RETI instruction is executed or the EMI bit and the related interrupt control bit are set both to 1 (if the stack is not full). To return from the interrupt subroutine, RET or RETI may be invoked. RETI sets the EMI bit and enables an interrupt service, but RET does not. Interrupts occurring in the interval between the rising edges of two consecutive T2 pulses are serviced on the latter of the two T2 pulses if the corresponding interrupts are enabled. In the case of simultaneous requests, the priorities in the following table apply. These can be masked by resetting the EMI bit. Interrupt Source External interrupt 0 External interrupt 1 Timer/Event Counter 0 overflow Timer/Event Counter 1 overflow Time base interrupt Real time clock interrupt Function Controls the master (global) interrupt (1=enabled; 0=disabled) Controls the external interrupt 0 (1=enabled; 0=disabled) Controls the external interrupt 1 (1=enabled; 0=disabled) Controls the Timer/Event Counter 0 interrupt (1=enabled; 0=disabled) External interrupt 0 request flag (1=active; 0=inactive) External interrupt 1 request flag (1=active; 0=inactive) Internal Timer/Event Counter 0 request flag (1=active; 0=inactive) Unused bit, read as 0 INTC0 (0BH) Register Bit No. 0 1 2 3 4 5 6 7 Label ET1I ETBI ERTI 3/4 T1F TBF RTF 3/4 Function Controls the Timer/Event Counter 1 interrupt (1=enabled; 0=disabled) Controls the time base interrupt (1=enabled; 0:disabled) Controls the real time clock interrupt (1=enabled; 0:disabled) Unused bit, read as 0 Internal Timer/Event Counter 1 request flag (1=active; 0=inactive) Time base request flag (1=active; 0=inactive) Real time clock request flag (1=active; 0=inactive) Unused bit, read as 0 INTC1 (1EH) Register Rev. 2.10 12 April 24, 2006 Priority 1 2 3 4 5 6 Vector 04H 08H 0CH 10H 14H 18H
Bit No. 0 1 2 3 4 5 6 7
Label EMI EEI0 EEI1 ET0I EIF0 EIF1 T0F 3/4
HT49R50A-1/HT49C50-1/HT49C50L
The Timer/Event Counter 0 interrupt request flag (T0F), external interrupt 1 request flag (EIF1), external interrupt 0 request flag (EIF0), enable Timer/Event Counter 0 interrupt bit (ET0I), enable external interrupt 1 bit (EEI1), enable external interrupt 0 bit (EEI0), and enable master interrupt bit (EMI) make up of the Interrupt Control register 0 (INTC0) which is located at 0BH in the RAM. The real time clock interrupt request flag (RTF), time base interrupt request flag (TBF), Timer/Event Counter 1 interrupt request flag (T1F), enable real time clock interrupt bit (ERTI), and enable time base interrupt bit (ETBI), enable Timer/Event Counter 1 interrupt bit (ET1I) on the other hand, constitute the Interrupt Control register 1 (INTC1) which is located at 1EH in the RAM. EMI, EEI0, EEI1, ET0I, ET1I, ETBI, and ERTI are all used to control the enable/disable status of interrupts. These bits prevent the requested interrupt from being serviced. Once the interrupt request flags (RTF, TBF, T0F, T1F, EIF1, EIF0) are all set, they remain in the INTC1 or INTC0 respectively until the interrupts are serviced or cleared by a software instruction. It is recommended that a program not use the CALL subroutine within the interrupt subroutine. Its because interrupts often occur in an unpredictable manner or require to be serviced immediately in some applications. At this time, if only one stack is left, and enabling the interrupt is not well controlled, operation of the call in the interrupt subroutine may damage the original control sequence. Oscillator Configuration These devices provide three oscillator circuits for system clocks, i.e., RC oscillator and crystal oscillator, determined by option. No matter what type of oscillator is selected, the signal is used for the system clock. The HALT mode stops the system oscillator and ignores external signal to conserve power. Of the three oscillators, if the RC oscillator is used, an external resistor between OSC1 and VSS is required, and the range of the resistance should be from 24kW to 1MW for HT49R50A-1/HT49C50-1 and from 560kW to 1MW for HT49C50L. The system clock, divided by 4, is available on OSC2 with pull-high resistor, which can be used to synchronize external logic. The RC oscillator provides the most cost effective solution. However, the frequency of the oscillation may vary with VDD, temperature, and the chip itself due to process variations. It is therefore, not suitable for timing sensitive operations where accurate oscillator frequency is desired. On the other hand, if the crystal oscillator is selected, a crystal across OSC1 and OSC2 is needed to provide the feedback and phase shift required for the oscillator, and no other external components are required. A resonator may be connected between OSC1 and OSC2 to replace the crystal and to get a frequency reference, but two external capacitors in OSC1 and OSC2 are required. Rev. 2.10 13
V
DD
OSC1 V
DD
OSC1
OSC2 C r y s ta l O s c illa to r
fS
YS
/4
OSC2 RC O s c illa to r
System Oscillator
OSC3
OSC4
32768Hz Crystal/RTC Oscillator There is another oscillator circuit designed for the real time clock. In this case, only the 32.768kHz crystal oscillator can be applied. The crystal should be connected between OSC3 and OSC4, and two external capacitors along with one external resistor are required for the oscillator circuit in order to get a stable frequency. The RTC oscillator circuit can be controlled to oscillate quickly by setting the QOSC bit (bit 4 of RTCC). It is recommended to turn on the quick oscillating function upon power on, and turn it off after 2 seconds. The WDT oscillator is a free running on-chip RC oscillator, and no external components are required. Although the system enters the power down mode, the system clock stops, and the WDT oscillator still works with a period of approximately 65ms at 5V. The WDT oscillator can be disabled by option to conserve power. Watchdog Timer - WDT The WDT clock source is implemented by a dedicated RC oscillator (WDT oscillator) or an instruction clock (system clock/4) or a real time clock oscillator (RTC oscillator). The timer is designed to prevent a software malfunction or sequence from jumping to an unknown location with unpredictable results. The WDT can be disabled by option. But if the WDT is disabled, all executions related to the WDT lead to no operation. The WDT time-out period is as fS/216~fS/215. If the WDT clock source chooses the internal WDT oscillator, the time-out period may vary with temperature, VDD, and process variations. On the other hand, if the clock source selects the instruction clock and the HALT instruction is executed, WDT may stop counting and lose its protecting purpose, and the logic can only be restarted by an external logic.
April 24, 2006
HT49R50A-1/HT49C50-1/HT49C50L
S y s te m C lo c k /4 O p tio n S e le c t fS D iv id e r P r e s c a le r CK R W D T C le a r T CK R T
RTC 32768H z OSC W DT 12kH z OSC
T im e - o u t R e s e t fS /2 16 ~ fS /2 15
Watchdog Timer When the device operates in a noisy environment, using the on-chip RC oscillator (WDT OSC) is strongly recommended, since the HALT can stop the system clock. The WDT overflow under normal operation initializes a chip reset and sets the status bit TO. In the HALT mode, the overflow initializes a warm reset, and only the program counter and SP are reset to zero. To clear the contents of the WDT, there are three methods to be adopted, i.e., external reset (a low level to RES), software instruction, and a HALT instruction. There are two types of software instructions; CLR WDT and the other set - CLR WDT1 and CLR WDT2. Of these two types of instruction, only one type of instruction can be active at a time depending on the options - CLR WDT times selection option. If the CLR WDT is selected (i.e., CLR WDT times equal one), any execution of the CLR WDT instruction clears the WDT. In the case that CLR WDT1 and CLR WDT2 are chosen (i.e., CLR WDT times equal two), these two instructions have to be executed to clear the WDT; otherwise, the WDT may reset the chip due to time-out. Multi-function Timer These devices provide a multi-function timer for the WDT, time base and RTC but with different time-out periods. The multi-function timer consists of a 7-stage divider and an 8-bit prescaler, with the clock source coming from the WDT OSC or RTC OSC or the instruction clock (i.e., system clock divided by 4). The multi-function timer also provides a selectable frequency signal (ranges from fS/22 to fS/28) for LCD driver circuits, and a selectable frequency signal (ranges from fS/22 to fS/29) for the buzzer output by option. It is recommended to select a near 4kHz signal to LCD driver circuits for proper display. Time Base The time base offers a periodic time-out period to generate a regular internal interrupt. Its time-out period ranges from fS/212 to fS/215 selected by options. If time base time-out occurs, the related interrupt request flag (TBF; bit 5 of INTC1) is set. But if the interrupt is enabled, and the stack is not full, a subroutine call to location 14H occurs. The time base time-out signal also can be applied to be a clock source of Timer/Event Counter 1 for getting a longer timer-out period. Note: * not recommended to be used
fS D iv id e r RT2 RT1 RT0 P r e s c a le r
fS
D iv id e r
P r e s c a le r
O p tio n
O p tio n
LCD
D r iv e r ( fS /2
2
2
~ fS /2
9
8
)
T im e B a s e In te r r u p t (fS /2
12
B u z z e r (fS /2
~ fS /2
)
~ fS /2
15
)
Time Base Real Time Clock - RTC The real time clock (RTC) is operated in the same manner as the time base that is used to supply a regular internal interrupt. Its time-out period ranges from fS/28 to fS/215 by software programming . Writing data to RT2, RT1 and RT0 (bit2, 1, 0 of RTCC;09H) yields various time-out periods. If the RTC time-out occurs, the related interrupt request flag (RTF; bit 6 of INTC1) is set. But if the interrupt is enabled, and the stack is not full, a subroutine call to location 18H occurs. The real time clock time-out signal also can be applied to be a clock source of Timer/Event Counter 0 for getting a longer time-out period. RT2 0 0 0 0 1 1 1 1 RT1 0 0 1 1 0 0 1 1 RT0 0 1 0 1 0 1 0 1 RTC Clock Divided Factor 28* 29* 210* 211* 212 213 214 215
8 to 1 M ux.
fS /2 ~ fS /2 R T C In te rru p t
12
15
Real Time Clock
Rev. 2.10
14
April 24, 2006
HT49R50A-1/HT49C50-1/HT49C50L
Power Down Operation - HALT The HALT mode is initialized by the HALT instruction and results in the following.
* The system oscillator turns off but the WDT oscillator
Reset There are three ways in which reset may occur.
* RES is reset during normal operation * RES is reset during HALT * WDT time-out is reset during normal operation
keeps running (if the WDT oscillator or the real time clock is selected).
* The contents of the on-chip RAM and of the registers
remain unchanged.
* The WDT is cleared and start recounting (if the WDT
clock source is from the WDT oscillator or the real time clock oscillator).
* All I/O ports maintain their original status. * The PDF flag is set but the TO flag is cleared. * LCD driver is still running (if the WDT OSC or RTC
OSC is selected). The system quits the HALT mode by an external reset, an interrupt, an external falling edge signal on port A, or a WDT overflow. An external reset causes device initialization, and the WDT overflow performs a warm reset. After examining the TO and PDF flags, the reason for chip reset can be determined. The PDF flag is cleared by system power-up or by executing the CLR WDT instruction, and is set by executing the HALT instruction. On the other hand, the TO flag is set if WDT time-out occurs, and causes a wake-up that only resets the program counter and SP, and leaves the others at their original state. The port A wake-up and interrupt methods can be considered as a continuation of normal execution. Each pin in port A can be independently selected to wake-up the device by option. Awakening from an I/O port stimulus, the program resumes execution of the next instruction. On the other hand, awakening from an interrupt, two sequences may occur. If the related interrupt is disabled or the interrupt is enabled but the stack is full, the program resumes execution at the next instruction. But if the interrupt is enabled, and the stack is not full, the regular interrupt response takes place. When an interrupt request flag is set before entering the HALT status, the system cannot be awaken using that interrupt. If wake-up events occur, it takes 1024 tSYS (system clock period) to resume normal operation. In other words, a dummy period is inserted after the wake-up. If the wake-up results from an interrupt acknowledgment, the actual interrupt subroutine execution is delayed by more than one cycle. However, if the Wake-up results in the next instruction execution, the execution will be performed immediately after the dummy period is finished. To minimize power consumption, all the I/O pins should be carefully managed before entering the HALT status.
The WDT time-out during HALT differs from other chip reset conditions, for it can perform a warm reset that resets only the program counter and SP and leaves the other circuits at their original state. Some registers remain unaffected during any other reset conditions. Most registers are reset to the initial condition once the reset conditions are met. Examining the PDF and TO flags, the program can distinguish between different chip resets. Note: * Make the length of the wiring, which is connected to the RES pin as short as possible, to avoid noise interference. PDF 0 u 1 u 1 RESET Conditions RES reset during power-up RES reset during normal operation RES Wake-up HALT WDT time-out during normal operation WDT Wake-up HALT
TO 0 u 0 1 1 Note:
u means unchanged
To guarantee that the system oscillator is started and stabilized, the SST (System Start-up Timer) provides an extra-delay of 1024 system clock pulses when the system awakes from the HALT state. Awaking from the HALT state, the SST delay is added. An extra SST delay is added during the power-up period and any wakeup from the HALT may enable only the SST delay. The functional unit chip reset status is shown below. Program Counter Interrupt Prescaler, Divider WDT, RTC, Time base 000H Disabled Cleared Cleared. After master reset, WDT starts counting
Timer/Event Counter Off Input/output ports Stack Pointer Input mode Points to the top of the stack
Rev. 2.10
15
April 24, 2006
HT49R50A-1/HT49C50-1/HT49C50L
The states of the registers are summarized below: Register TMR0 TMR0C TMR1 TMR1C Program Counter MP0 MP1 BP ACC TBLP TBLH STATUS INTC0 INTC1 RTCC PA PB PC Note: Reset (Power On) xxxx xxxx 0000 1--xxxx xxxx 0000 1--000H xxxx xxxx xxxx xxxx ---- ---0 xxxx xxxx xxxx xxxx -xxx xxxx --00 xxxx -000 0000 -000 -000 --00 0111 1111 1111 xxxx xxxx ---- 1111 * refers to warm reset u means unchanged x means unknown WDT Time-out RES Reset (Normal Operation) (Normal Operation) xxxx xxxx 0000 1--xxxx xxxx 0000 1--000H uuuu uuuu uuuu uuuu ---- ---0 uuuu uuuu uuuu uuuu -uuu uuuu --1u uuuu -000 0000 -000 -000 --00 0111 1111 1111 xxxx xxxx ---- 1111 xxxx xxxx 0000 1--xxxx xxxx 0000 1--000H uuuu uuuu uuuu uuuu ---- ---0 uuuu uuuu uuuu uuuu -uuu uuuu --uu uuuu -000 0000 -000 -000 --00 0111 1111 1111 xxxx xxxx ---- 1111 RES Reset (HALT) xxxx xxxx 0000 1--xxxx xxxx 0000 1--000H uuuu uuuu uuuu uuuu ---- ---0 uuuu uuuu uuuu uuuu -uuu uuuu --01 uuuu -000 0000 -000 -000 --00 0111 1111 1111 xxxx xxxx ---- 1111 WDT Time-out (HALT)* uuuu uuuu uuuu u--uuuu uuuu uuuu u--000H uuuu uuuu uuuu uuuu ---- ---u uuuu uuuu uuuu uuuu -uuu uuuu --11 uuuu -uuu uuuu -uuu -uuu --uu uuuu uuuu uuuu uuuu uuuu ---- uuuu
V
DD
VDD
0 .0 1 m F * 100kW RES 10kW 0 .1 m F *
RES S S T T im e - o u t C h ip R eset
tS
ST
Reset Timing Chart
Reset Circuit
H ALT W DT W DT T im e - o u t R eset E x te rn a l
W a rm
R eset
RES SST 1 0 - b it R ip p le C o u n te r P o w e r - o n D e te c tio n
OSC1
C o ld R eset
Reset Configuration
Rev. 2.10
16
April 24, 2006
HT49R50A-1/HT49C50-1/HT49C50L
Timer/Event Counter Two timer/event counters are implemented in the devices. Both of them contain an 8-bit programmable count-up counter. The timer/event counter 0 clock source may come from the system clock or system clock/4 or RTC time-out signal or external source. System clock source or system clock/4 is selected by option. The timer/event counter 1 clock source may come from TMR0 overflow or system clock or time base time-out signal or system clock/4 or external source, and the three former clock source is selected by option. Using external clock input allows the user to count external events, measure time internals or pulse widths, or generate an accurate time base. While using the internal clock allows the user to generate an accurate time base. The two timer/event counters are operated almost in the same manner, except the clock source and related registers.
S y s te m S y s te m C lo c k C lo c k /4
There are two registers related to the Timer/Event Counter 0, i.e., TMR0 ([0DH]) and TMR0C ([0EH]), and two registers related to the Timer/Event Counter 1, i.e., TMR1 ([10H], and TMR1C ([11H]). There are also two physical registers are mapped to TMR0 (TMR1) location; writing TMR0 (TMR1) places the starting value in the timer/event counter preload register, while reading it yields the contents of the timer/event counter. TMR0C and TMR1C are timer/event counter control registers used to define some options. The T0M0 and T0M1 (T1M0 and T1M1) bits define the operation mode. The event count mode is used to count external events, which means that the clock source is from an external (TMR0, TMR1) pin. The timer mode functions as a normal timer with the clock source coming from the internal selected clock source. Finally, the pulse width measurement mode can be used to count the high or low level duration of the external signal (TMR0, TMR1), and the counting is based on the internal selected clock source.
O p tio n S e le c t M U X
R TC O ut T0S TM R0 T0E T0M 1 T0M 0 T0O N
D a ta b u s T0M 1 T0M 0 T im e r /E v e n t C o u n te r 0 P r e lo a d R e g is te r R e lo a d
P u ls e W id th M e a s u re m e n t M o d e C o n tro l
T im e r /E v e n t C o u n te r 0 PFD0
O v e r flo w T o In te rru p t
Timer/Event Counter 0
T M R 0 O v e r flo w S y s te m C lo c k O p tio n S e le c t M U X D a ta b u s T1S TM R1 T1E T1M 1 T1M 0 T1O N P u ls e W id th M e a s u re m e n t M o d e C o n tro l T im e r /E v e n t C o u n te r 1 PFD1 O v e r flo w T o In te rru p t T1M 1 T1M 0 T im e r /E v e n t C o u n te r 1 P r e lo a d R e g is te r R e lo a d
T im e B a s e O u t S y s te m C lo c k /4
Timer/Event Counter 1
PFD0 M PFD1
U X
1 /2
PFD
P A 3 D a ta C T R L PFD S o u r c e O p tio n
PFD Source Option
Rev. 2.10
17
April 24, 2006
HT49R50A-1/HT49C50-1/HT49C50L
Bit No. 0~2 Label 3/4 Unused bit, read as 0 Defines the TMR0 active edge of the timer/event counter: In Event Counter Mode (T0M1,T0M0)=(0,1): 1:count on falling edge; 0:count on rising edge In Pulse Width measurement mode (T0M1,T0M0)=(1,1): 1: start counting on the rising edge, stop on the falling edge; 0: start counting on the falling edge, stop on the rising edge To enable/disable timer counting (0=disabled; 1=enabled) 2 to 1 multiplexer control inputs to select the timer/event counter clock source (0=RTC outputs; 1= system clock or system clock/4) To define the operating mode (T0M1, T0M0) 01=Event count mode (External clock) 10=Timer mode (Internal clock) 11=Pulse Width measurement mode (External clock) 00=Unused TMR0C (0EH) Register Bit No. 0~2 Label 3/4 Unused bit, read as 0 Defines the TMR1 active edge of the timer/event counter: In Event Counter Mode (T1M1,T1M0)=(0,1): 1:count on falling edge; 0:count on rising edge In Pulse Width measurement mode (T1M1,T1M0)=(1,1): 1: start counting on the rising edge, stop on the falling edge; 0: start counting on the falling edge, stop on the rising edge To enable/disable timer counting (0= disabled; 1= enabled) 2 to 1 multiplexer control inputs to select the timer/event counter clock source (0= options clock source; 1= system clock/4) To define the operating mode (T1M1, T1M0) 01= Event count mode (External clock) 10= Timer mode (Internal clock) 11= Pulse Width measurement mode (External clock) 00= Unused TMR1C (11H) Register In the event count or timer mode, the timer/event counter starts counting at the current contents in the timer/event counter and ends at FFH. Once an overflow occurs, the counter is reloaded from the timer/event counter preload register, and generates an interrupt request flag (T0F;bit 6 of INTC0, T1F;bit 4 of INTC1). In the pulse width measurement mode with the values of the T0ON/T1ON and T0E/T1E bits equal to one, after the TMR0 (TMR1) has received a transient from low to high (or high to low if the T0E/T1E bit is 0), it will start counting until the TMR0 (TMR1) returns to the original level and resets the T0ON/T1ON. The measured result remains in the timer/event counter even if the activated transient occurs again. In other words, only one cycle measurement can be made until the T0ON/T1ON is set. The cycle measurement will re-function as long as it receives further transient pulse. In this operation mode, the timer/event counter begins counting according not to the logic level but to the transient edges. In the case of counter overflows, the counter is reloaded from the timer/event counter preload register and issues an interrupt request, as in the other two modes, i.e., event and timer modes. To enable the counting operation, the Timer ON bit (T0ON: bit 4 of TMR0C; T1ON: bit 4 of TMR1C) should be set to 1. In the pulse width measurement mode, the T0ON/T1ON is automatically cleared after the measurement cycle is completed. But in the other two modes, the T0ON/T1ON can only be reset by instructions. The Function Function
3
T0E
4 5
T0ON T0S
6 7
T0M0 T0M1
3
T1E
4 5
T1ON T1S
6 7
T1M0 T1M1
Rev. 2.10
18
April 24, 2006
HT49R50A-1/HT49C50-1/HT49C50L
overflow of the Timer/Event Counter 0/1 is one of the wake-up sources and can also be applied to a PFD (Programmable Frequency Divider) output at PA3 by option. Only one PFD (PFD0 or PFD1) can be applied to PA3 by options. If PA3 is set as PFD output, there are two types of selections; One is PFD0 as the PFD output, the other is PFD1 as the PFD output. PFD0, PFD1 are the timer overflow signals of the Timer/Event Counter 0, Timer/Event Counter 1 respectively. No matter what the operation mode is, writing a 0 to ET0I or ET1I disables the related interrupt service. When the PFD function is selected, executing CLR [PA].3 instruction to enable PFD output and executing SET [PA].3 instruction to disable PFD output. In the case of timer/event counter OFF condition, writing data to the timer/event counter preload register also reloads that data to the timer/event counter. But if the timer/event counter is turn on, data written to the timer/event counter is kept only in the timer/event counter preload register. The timer/event counter still continues its operation until an overflow occurs. When the timer/event counter (reading TMR0/TMR1) is read, the clock is blocked to avoid errors. As this may results in a counting error, blocking of the clock should be taken into account by the programmer. It is strongly recommended to load a desired value into the TMR0/TMR1 register first, then turn on the related timer/event counter for proper operation. Because the initial value of TMR0/TMR1 is unknown. Due to the timer/event scheme, the programmer should pay special attention on the instruction to enable then disable the timer for the first time, whenever there is a need to use the timer/event function, to avoid unpredicatable result. After this procedure, the timer/event function can be operated normally. The example given below, using two 8-bit width Timers (timer 0 ;timer 1) cascade into 16-bit width. START: mov mov a, 09h ; Set ET0I & EMI bits to intc0, a ; enable timer 0 and ; global interrupt
mov a, 01h ; Set ET1I bit to enable mov intc1, a ; timer 1 interrupt mov a, 80h ; Set operating mode as mov tmr1c, a ; timer mode and select mask ; option clock source mov a, 0a0h ; Set operating mode as timer mov tmr0c, a ; mode and select system ; clock/4
set clr
tmr1c.4 ; Enable then disable timer 1 tmr1c.4 ; for the first time
mov mov mov mov
a, 00h tmr0, a a, 00h tmr1, a
; Load a desired value into ; the TMR0/TMR1 register ; ; ; Normal operating ;
set tmr0c.4 set tmr1c.4 END
Input/Output Ports There are a 12-bit bidirectional input/output port, an 8-bit input port in the devices, labeled PA, PB and PC which are mapped to [12H], [14H] and [16H] of the RAM, respectively. PA0~PA3 can be configured as CMOS (output) or NMOS (input/output) with or without pull-high resistor by option. PA4~PA7 are always pull-high and NMOS (input/output). If you choose NMOS (input), Each pin on the port (PA0~PA7) can be configured as a wake-up input. PB can only be used for input operation. The contents of PC4~PC7 are unknown. PC can be configured as CMOS output or NMOS input/output with or without pull-high resistor by option. All the port for the input operation (PA, PB and PC), these ports are non-latched, that is, the inputs should be ready at the T2
V V
DD DD
W eak P u ll- u p O p tio n (P A 0 ~ P A 3 , P C ) PA0~PA7 PC 0~PC 3
D a ta b u s D W r ite C h ip R e s e t
Q CK S Q
O p tio n (P A 0 ~ PA3,PC )
R e a d I/O S y s te m W a k e - u p ( P A o n ly ) O p tio n
PA, PC Input/Output Ports
Rev. 2.10
19
April 24, 2006
HT49R50A-1/HT49C50-1/HT49C50L
V
DD
W eak P u ll- u p
user wants to use the BZ/BZ or PFD function, the related PA port should be set as a CMOS output. The buzzer output signals are controlled by PA0 and PA1 data registers and defined in the following table.
PB0~PB7
D a ta b u s R e a d I/O
PA1 Data Register 0 1 X
PA0 Data Register 0 0 1
PA0/PA1 Pad State PA0=BZ, PA1=BZ PA0=BZ, PA1=0 PA0=0, PA1=0
PB Input Ports rising edge of the instruction MOV A, [m] (m=12H or 14H). For PA, PC output operation, all data are latched and remain unchanged until the output latch is rewritten. When the PA and PC structures are open drain NMOS type, it should be noted that, before reading data from the pads, a 1 should be written to the related bits to disable the NMOS device. That is executing first the instruction SET [m].i (i=0~7 for PA) to disable related NMOS device, and then MOV A, [m] to get stable data. After chip reset, these input lines remain at the high level or are left floating (by options). Each pin of these output latches can be set or cleared by the MOV [m], A (m=12H or 16H) instruction. Some instructions first input data and then follow the output operations. For example, SET [m].i, CLR [m].i, CPL [m], CPLA [m] read the entire port states into the CPU, execute the defined operations (bit-operation), and then write the results back to the latches or to the accumulator. When a PA or PC line is used as an I/O line, the related PA or PC line options should be configured as NMOS with or without pull-high resistor. Once a PA or PC line is selected as a CMOS output, the I/O function cannot be used. The input state of a PA or PC line is read from the related PA or PC pad. When the PA or PC is configured as NMOS with or without pull-high resistor, one should be careful when applying a read-modify-write instruction to PA or PC. Since the read-modify-write will read the entire port state (pads state) firstly, execute the specified instruction and then write the result to the port data register. When the read operation is executed, a fault pad state (caused by the load effect or floating state) may be read. Errors will then occur. There are three function pins that share with the PA port: PA0/BZ, PA1/BZ and PA3/PFD. The BZ and BZ are buzzer driving output pair and the PFD is a programmable frequency divider output. If the Timer OFF OFF ON ON Note: Timer Preload Value X X N N X stands for undefined U stands for unknown 20
Note: X stands for undefined The PFD output signal function is controlled by the PA3 data register and the timer/event counter state. The PFD output signal frequency is also dependent on the timer/event counter overflow period. The definitions of PFD control signal and PFD output frequency are listed in the following table. LCD Display Memory The devices provides an area of embedded data memory for LCD display. This area is located from 40H to 60H of the RAM at Bank 1. Bank pointer (BP; located at 04H of the RAM) is the switch between the RAM and the LCD display memory. When the BP is set as 1, any data written into 40H~60H will effect the LCD display. When the BP is cleared to 0, any data written into 40H~60H means to access the general purpose data memory. The LCD display memory can be read and written to only by indirect addressing mode using MP1. When data is written into the display data area, it is automatically read by the LCD driver which then generates the corresponding LCD driving signals. To turn the display on or off, a 1 or a 0 is written to the corresponding bit of the display memory, respectively. The figure illustrates the mapping between the display memory and LCD pattern for the devices.
COM 0 1 2 2 3 3 40H 41H 42H 43H 5EH 5FH 60H B it 0 1
SEGMENT
0
1
2
3
30
31
32
Display Memory PA3 Pad State U 0 PFD 0 PFD Frequency X X fINT/[2(256-N)] X
PA3 Data Register 0 1 0 1
Rev. 2.10
April 24, 2006
HT49R50A-1/HT49C50-1/HT49C50L
LCD Driver Output The output number of the LCD driver device can be 322, 333 or 324 by option (i.e., 1/2 duty, 1/3 duty or 1/4 duty). The bias type LCD driver can be R type or C type for HT49R50A-1/HT49C50-1 while the bias type LCD driver can only be C type for HT49C50L. If the R bias type is selected, no external capacitor is required. If the C bias type is selected, a capacitor mounted between C1 and C2 pins is needed. The LCD driver bias voltage for HT49R50A-1/HT49C50-1 can be 1/2 bias or 1/3 bias by option, while the LCD driver bias voltage for HT49C50L can only be 1/2 bias. If 1/2 bias is selected, a capacitor mounted between V2 pin and ground is required. If 1/3 bias is selected, two capacitors are needed for V1 and V2 pins. LCD bias power supply selection for HT49R50A-1/ HT49C50-1: There are two types of selections: 1/2 bias or 1/3 bias. LCD bias type selection for HT49R50A-1/HT49C50-1: This option is to determine what kind of bias is selected, R type or C type. Low Voltage Reset/Detector Functions There is a low voltage detector (LVD) and a low voltage reset circuit (LVR) implemented in the microcontroller. These two functions can be enabled/disabled by options. Once the options of LVD is enabled, the user can use the RTCC.3 to enable/disable (1/0) the LVD circuit and read the LVD detector status (0/1) from RTCC.5; otherwise, the LVD function is disabled. The LVR has the same effect or function with the external RES signal which performs chip reset. During HALT state, LVR is disabled.
D u r in g a r e s e t p u ls e C O M 0 ,C O M 1 ,C O M 2 A ll L C D d r iv e r o u tp u ts VA VB VSS VA VB VSS
N o r m a l o p e r a tio n m o d e
*
COM0 COM1 CO M 2* L C D s e g m e n ts O N C O M 0 ,1 ,2 s id e s a r e u n lig h te d O n ly L C D s e g m e n ts O N C O M 0 s id e a r e lig h te d O n ly L C D s e g m e n ts O N C O M 1 s id e a r e lig h te d O n ly L C D s e g m e n ts O N C O M 2 s id e a r e lig h te d L C D s e g m e n ts O N C O M 0 ,1 s id e s a r e lig h te d L C D s e g m e n ts O N C O M 0 ,2 s id e s a r e lig h te d L C D s e g m e n ts O N C O M 1 ,2 s id e s a r e lig h te d L C D s e g m e n ts O N C O M 0 ,1 ,2 s id e s a r e lig h te d HALT M ode C O M 0 ,C O M 1 ,C O M 2 * A ll L C D N o te : d r iv e r o u tp u ts
*
*
VA VB VS VA VB VS VA VB VS VA VB VS VA VB VS VA VB VS VA VB VS VA VB VS VA VB VS VA VB VS VA VB VS S VA VB VSS VA VB VSS
S S S S S S S S S S
" * " O m it th e C O M 2 s ig n a l, if th e 1 /2 d u ty L C D is u s e d . V A = V L C D , V B = 1 /2 V L C D fo r H T 4 9 R 5 0 A -1 /H T 4 9 C 5 0 -1 V A = 2 V 2 , V B = V 2 , C ty p e fo r H T 4 9 C 5 0 L
LCD Driver Output (1/3 Duty, 1/2 Bias, R/C Type) Rev. 2.10 21 April 24, 2006
HT49R50A-1/HT49C50-1/HT49C50L
VA COM0 VB VC VSS VA VB COM1 VC VSS VA COM2 VB VC VSS VA VB COM3 VC VSS VA L C D s e g m e n ts O N C O M 2 s id e lig h te d VB VC VSS
N o te : 1 /4 d u ty , 1 /3 b ia s , C 1 /4 d u ty , 1 /3 b ia s , R
ty p e : " V A " 3 /2 V L C D , " V B " V L C D , " V C " 1 /2 V L C D ty p e : "V A " V L C D , "V B " 2 /3 V L C D , "V C " 1 /3 V L C D
1 /3 b ia s o n ly fo r H T 4 9 R 5 0 A - 1 /H T 4 9 C 5 0 - 1
LCD Driver Output (1/4 Duty, 1/3 Bias, C Type)
The RTCC register definitions are listed in the table on the next page. Bit No. 0~2 3 4 5 6, 7 Label RT0~RT2 LVDC* QOSC LVDO* 3/4 Read/Write R/W R/W R/W R 3/4 Reset 111B 0 0 0 3/4 Function 8 to 1 multiplexer control inputs to select the real clock prescaler output LVD enable/disable (1/0) 32768Hz OSC quick start-up oscillating 0/1: quickly/slowly start LVD detection output (1/0) 1: low voltage detected Unused bit, read as 0
Note: * For HT49R50A-1/HT49C50-1 RTCC (09H) Register
Rev. 2.10
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HT49R50A-1/HT49C50-1/HT49C50L
Options The following shows the options in the devices. All these options should be defined in order to ensure proper system functioning. Options OSC type selection. This option is to determine whether an RC or Crystal or 32768Hz crystal oscillator is chosen as system clock. WDT Clock source selection. RTC and Time Base. There are three types of selection: system clock/4 or RTC OSC or WDT OSC. WDT enable/disable selection. WDT can be enabled or disabled by options. CLR WDT times selection. This option defines how to clear the WDT by instruction. One time means that the CLR WDT can clear the WDT. Two times means that if both of the CLR WDT1 and CLR WDT2 have been executed, only then will the WDT be cleared. Time Base time-out period selection. The Time Base time-out period ranges from clock/212 to clock/215. Clock means the clock source selected by options. Buzzer output frequency selection. There are eight types of frequency signals for buzzer output: Clock/22~Clock/29. Clock means the clock source selected by options. Wake-up selection. This option defines the wake-up capability. External I/O pins (PA only) all have the capability to wake-up the chip from a HALT by a falling edge. Pull-high selection. This option is to decide whether the pull-high resistance is visible or not on the PA0~PA3 and PC. (PB and PA4~PA7 are always pull-high) PA0~PA3 and PC CMOS or NMOS selection. The structure of PA0~PA3 and PC each 4 bits can be selected as CMOS or NMOS individually. When the CMOS is selected, the related pins only can be used for output operations. When the NMOS is selected, the related pins can be used for input or output operations. (PA4~PA7 are always NMOS) Clock source selection of Timer/Event Counter 0. There are two types of selection: system clock or system clock/4. Clock source selection of Timer/Event Counter 1. There are three types of selection: TMR0 overflow, system clock or Time Base overflow. I/O pins share with other functions selection. PA0/BZ, PA1/BZ: PA0 and PA1 can be set as I/O pins or buzzer outputs. PA3/PFD: PA3 can be set as I/O pins or PFD output. LCD common selection. There are three types of selection: 2 common (1/2 duty) or 3 common (1/3 duty) or 4 common (1/4 duty). If the 4 common is selected, the segment output pin SEG32 will be set as a common output. LCD bias power supply selection. There are two types of selection: 1/2 bias or 1/3 bias for HT49R50A-1/HT49C50-1. LCD bias type selection. This option is to decide what kind of bias is selected, R type or C type for HT49R50A-1/HT49C50-1. LCD driver clock selection. There are seven types of frequency signals for the LCD driver circuits: fS/22~fS/28. fS means the clock source selection by options. LCD ON/OFF at HALT selection LVR selection. LVR has enable or disable options LVD selection. LVD has enable or disable options PFD selection. If PA3 is set as PFD output, there are two types of selection; One is PFD0 as the PFD output, the other is PFD1 as the PFD output. PFD0, PFD1 are the timer overflow signals of the Timer/Event Counter 0, Timer/Event Counter 1 respectively.
Rev. 2.10
23
April 24, 2006
HT49R50A-1/HT49C50-1/HT49C50L
Application Circuits
For HT49R50A-1/HT49C50-1 Application Circuit
V
DD
0 .0 1 m F * 100kW 0 .1 m F
10kW
VDD RES
CO M 0~CO M 3 SEG 0~SEG 31
LCD PANEL
VLC D C1
LCD
P o w e r S u p p ly
0 .1 m F * VSS
0 .1 m F C2 V 0 .1 m F R V2 0 .1 m F C1
DD
OSC C ir c u it S e e r ig h t s id e 32768H z 10pF
OSC1 OSC2
V1
470pF
OSC
OSC1 fS
YS
R C S y s te m O s c illa to r 24kW /4
OSC2 OSC1 C ry s ta l S y s te m F o r th e v a lu e s , s e e ta b le b e lo w O s c illa to r
OSC3
PA0~PA7 PB0~PB7 PC 0~PC 3 IN T 0 IN T 1 TM R0 TM R1
C2 R1
OSC2
OSC4
OSC1
OSC2 OSC
32 Os OS un
7 6 8 H z C ry s ta l S y s te m c illa to r C 1 a n d O S C 2 le ft c o n n e c te d
H T 4 9 R 5 0 A -1 /H T 4 9 C 5 0 -1
C ir c u it
The following table shows the C1, C2 and R1 values corresponding to the different crystal values. (For reference only) Crystal or Resonator 4MHz Crystal 4MHz Resonator 3.58MHz Crystal 3.58MHz Resonator 2MHz Crystal & Resonator 1MHz Crystal 480kHz Resonator 455kHz Resonator 429kHz Resonator C1, C2 0pF 10pF 0pF 25pF 25pF 35pF 300pF 300pF 300pF R1 10kW 12kW 10kW 10kW 10kW 27kW 9.1kW 10kW 10kW
The function of the resistor R1 is to ensure that the oscillator will switch off should low voltage conditions occur. Such a low voltage, as mentioned here, is one which is less than the lowest value of the MCU operating voltage. Note however that if the LVR is enabled then R1 can be removed.
Note:
The resistance and capacitance for reset circuit should be designed in such a way as to ensure that the VDD is stable and remains within a valid operating voltage range before bringing RES to high. * Make the length of the wiring, which is connected to the RES pin as short as possible, to avoid noise interference.
Rev. 2.10
24
April 24, 2006
HT49R50A-1/HT49C50-1/HT49C50L
For HT49C50L Application Circuit
OSC3
CO M 0~CO M 3 SEG 0~SEG 31
LCD PANEL V
DD
OSC4
VLCD 0 .1 m F R
470pF
OSC
V
100kW
V
YS
OSC1
DD
R C S y s te m 560kW SC
O s c illa to r <1M W
DD
C1 0 .1 m F C2
RES 0 .1 m F
fS
/4
OSC2 OSC1 C ry s ta l S y s te m O s c illa to r
200pF
V1 0 .1 m F V2 V
DD
200pF OSC2
IN T 0 IN T 1 TM R0 TM R1 PA0~PA7 PB0~PB7 PC 0~PC 3 H T49C 50L
OSC1
OSC2 OSC
3 2 7 6 8 H z C ry s ta l S y s te m O s c illa to r O S C 1 a n d O S C 2 le ft u n c o n n e c te d
C ir c u it
Note:
The resistance and capacitance for reset circuit should be designed in such a way as to ensure that the VDD is stable and remains within a valid operating voltage range before bringing RES to high.
Rev. 2.10
25
April 24, 2006
HT49R50A-1/HT49C50-1/HT49C50L
Instruction Set Summary
Mnemonic Arithmetic ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m] DAA [m] Add data memory to ACC Add ACC to data memory Add immediate data to ACC Add data memory to ACC with carry Add ACC to data memory with carry Subtract immediate data from ACC Subtract data memory from ACC Subtract data memory from ACC with result in data memory Subtract data memory from ACC with carry Subtract data memory from ACC with carry and result in data memory Decimal adjust ACC for addition with result in data memory 1 1(1) 1 1 1(1) 1 1 1(1) 1 1(1) 1(1) Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV C Description Instruction Cycle Flag Affected
Logic Operation AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m] AND data memory to ACC OR data memory to ACC Exclusive-OR data memory to ACC AND ACC to data memory OR ACC to data memory Exclusive-OR ACC to data memory AND immediate data to ACC OR immediate data to ACC Exclusive-OR immediate data to ACC Complement data memory Complement data memory with result in ACC 1 1 1 1(1) 1(1) 1(1) 1 1 1 1(1) 1 Z Z Z Z Z Z Z Z Z Z Z
Increment & Decrement INCA [m] INC [m] DECA [m] DEC [m] Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Data Move MOV A,[m] MOV [m],A MOV A,x Bit Operation CLR [m].i SET [m].i Clear bit of data memory Set bit of data memory 1(1) 1(1) None None Move data memory to ACC Move ACC to data memory Move immediate data to ACC 1 1(1) 1 None None None Rotate data memory right with result in ACC Rotate data memory right Rotate data memory right through carry with result in ACC Rotate data memory right through carry Rotate data memory left with result in ACC Rotate data memory left Rotate data memory left through carry with result in ACC Rotate data memory left through carry 1 1(1) 1 1(1) 1 1(1) 1 1(1) None None C C None None C C Increment data memory with result in ACC Increment data memory Decrement data memory with result in ACC Decrement data memory 1 1(1) 1 1(1) Z Z Z Z
Rev. 2.10
26
April 24, 2006
HT49R50A-1/HT49C50-1/HT49C50L
Mnemonic Branch JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Table Read TABRDC [m] TABRDL [m] Miscellaneous NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT Note: No operation Clear data memory Set data memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles of data memory Swap nibbles of data memory with result in ACC Enter power down mode 1 1(1) 1(1) 1 1 1 1(1) 1 1 None None None TO,PDF TO(4),PDF(4) TO(4),PDF(4) None None TO,PDF Read ROM code (current page) to data memory and TBLH Read ROM code (last page) to data memory and TBLH 2(1) 2(1) None None Jump unconditionally Skip if data memory is zero Skip if data memory is zero with data movement to ACC Skip if bit i of data memory is zero Skip if bit i of data memory is not zero Skip if increment data memory is zero Skip if decrement data memory is zero Skip if increment data memory is zero with result in ACC Skip if decrement data memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt 2 1(2) 1(2) 1(2) 1(2) 1(3) 1(3) 1(2) 1(2) 2 2 2 2 None None None None None None None None None None None None None Description Instruction Cycle Flag Affected
x: Immediate data m: Data memory address A: Accumulator i: 0~7 number of bits addr: Program memory address O: Flag is affected -: Flag is not affected
(1)
: If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). : If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). Otherwise the original instruction cycle is unchanged. : and (2) : The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the CLR WDT1 or CLR WDT2 instruction, the TO and PDF are cleared. Otherwise the TO and PDF flags remain unchanged.
(2)
(3) (1) (4)
Rev. 2.10
27
April 24, 2006
HT49R50A-1/HT49C50-1/HT49C50L
Instruction Definition
ADC A,[m] Description Operation Affected flag(s) TO 3/4 ADCM A,[m] Description Operation Affected flag(s) TO 3/4 ADD A,[m] Description Operation Affected flag(s) TO 3/4 ADD A,x Description Operation Affected flag(s) TO 3/4 ADDM A,[m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O Add data memory and carry to the accumulator The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the accumulator. ACC ACC+[m]+C
Add the accumulator and carry to data memory The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the specified data memory. [m] ACC+[m]+C
Add data memory to the accumulator The contents of the specified data memory and the accumulator are added. The result is stored in the accumulator. ACC ACC+[m]
Add immediate data to the accumulator The contents of the accumulator and the specified data are added, leaving the result in the accumulator. ACC ACC+x
Add the accumulator to the data memory The contents of the specified data memory and the accumulator are added. The result is stored in the data memory. [m] ACC+[m]
Rev. 2.10
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April 24, 2006
HT49R50A-1/HT49C50-1/HT49C50L
AND A,[m] Description Operation Affected flag(s) TO 3/4 AND A,x Description Operation Affected flag(s) TO 3/4 ANDM A,[m] Description Operation Affected flag(s) TO 3/4 CALL addr Description PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 Logical AND accumulator with data memory Data in the accumulator and the specified data memory perform a bitwise logical_AND operation. The result is stored in the accumulator. ACC ACC AND [m]
Logical AND immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical_AND operation. The result is stored in the accumulator. ACC ACC AND x
Logical AND data memory with the accumulator Data in the specified data memory and the accumulator perform a bitwise logical_AND operation. The result is stored in the data memory. [m] ACC AND [m]
Subroutine call The instruction unconditionally calls a subroutine located at the indicated address. The program counter increments once to obtain the address of the next instruction, and pushes this onto the stack. The indicated address is then loaded. Program execution continues with the instruction at this address. Stack Program Counter+1 Program Counter addr TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation
Affected flag(s)
CLR [m] Description Operation Affected flag(s)
Clear data memory The contents of the specified data memory are cleared to 0. [m] 00H TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Rev. 2.10
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HT49R50A-1/HT49C50-1/HT49C50L
CLR [m].i Description Operation Affected flag(s) TO 3/4 CLR WDT Description Operation PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Clear bit of data memory The bit i of the specified data memory is cleared to 0. [m].i 0
Clear Watchdog Timer The WDT is cleared (clears the WDT). The power down bit (PDF) and time-out bit (TO) are cleared. WDT 00H PDF and TO 0 TO 0 PDF 0 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
CLR WDT1 Description
Preclear Watchdog Timer Together with CLR WDT2, clears the WDT. PDF and TO are also cleared. Only execution of this instruction without the other preclear instruction just sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged. WDT 00H* PDF and TO 0* TO 0* PDF 0* OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation
Affected flag(s)
CLR WDT2 Description
Preclear Watchdog Timer Together with CLR WDT1, clears the WDT. PDF and TO are also cleared. Only execution of this instruction without the other preclear instruction, sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged. WDT 00H* PDF and TO 0* TO 0* PDF 0* OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation
Affected flag(s)
CPL [m] Description Operation Affected flag(s)
Complement data memory Each pin of the specified data memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. [m] [m] TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4
Rev. 2.10
30
April 24, 2006
HT49R50A-1/HT49C50-1/HT49C50L
CPLA [m] Description Complement data memory and place result in the accumulator Each pin of the specified data memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. The complemented result is stored in the accumulator and the contents of the data memory remain unchanged. ACC [m] TO 3/4 DAA [m] Description PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4
Operation Affected flag(s)
Decimal-Adjust accumulator for addition The accumulator value is adjusted to the BCD (Binary Coded Decimal) code. The accumulator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD adjustment is done by adding 6 to the original value if the original value is greater than 9 or a carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored in the data memory and only the carry flag (C) may be affected. If ACC.3~ACC.0 >9 or AC=1 then [m].3~[m].0 (ACC.3~ACC.0)+6, AC1=AC else [m].3~[m].0 (ACC.3~ACC.0), AC1=0 and If ACC.7~ACC.4+AC1 >9 or C=1 then [m].7~[m].4 ACC.7~ACC.4+6+AC1,C=1 else [m].7~[m].4 ACC.7~ACC.4+AC1,C=C TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Operation
Affected flag(s)
DEC [m] Description Operation Affected flag(s)
Decrement data memory Data in the specified data memory is decremented by 1. [m] [m]-1 TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4
DECA [m] Description Operation Affected flag(s)
Decrement data memory and place result in the accumulator Data in the specified data memory is decremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged. ACC [m]-1 TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4
Rev. 2.10
31
April 24, 2006
HT49R50A-1/HT49C50-1/HT49C50L
HALT Description Enter power down mode This instruction stops program execution and turns off the system clock. The contents of the RAM and registers are retained. The WDT and prescaler are cleared. The power down bit (PDF) is set and the WDT time-out bit (TO) is cleared. Program Counter Program Counter+1 PDF 1 TO 0 TO 0 INC [m] Description Operation Affected flag(s) TO 3/4 INCA [m] Description Operation Affected flag(s) TO 3/4 JMP addr Description Operation Affected flag(s) TO 3/4 MOV A,[m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Directly jump The program counter are replaced with the directly-specified address unconditionally, and control is passed to this destination. Program Counter addr PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 1 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation
Affected flag(s)
Increment data memory Data in the specified data memory is incremented by 1 [m] [m]+1
Increment data memory and place result in the accumulator Data in the specified data memory is incremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged. ACC [m]+1
Move data memory to the accumulator The contents of the specified data memory are copied to the accumulator. ACC [m]
Rev. 2.10
32
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HT49R50A-1/HT49C50-1/HT49C50L
MOV A,x Description Operation Affected flag(s) TO 3/4 MOV [m],A Description Operation Affected flag(s) TO 3/4 NOP Description Operation Affected flag(s) TO 3/4 OR A,[m] Description Operation Affected flag(s) TO 3/4 OR A,x Description Operation Affected flag(s) TO 3/4 ORM A,[m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 No operation No operation is performed. Execution continues with the next instruction. Program Counter Program Counter+1 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Move immediate data to the accumulator The 8-bit data specified by the code is loaded into the accumulator. ACC x
Move the accumulator to data memory The contents of the accumulator are copied to the specified data memory (one of the data memories). [m] ACC
Logical OR accumulator with data memory Data in the accumulator and the specified data memory (one of the data memories) perform a bitwise logical_OR operation. The result is stored in the accumulator. ACC ACC OR [m]
Logical OR immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical_OR operation. The result is stored in the accumulator. ACC ACC OR x
Logical OR data memory with the accumulator Data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_OR operation. The result is stored in the data memory. [m] ACC OR [m]
Rev. 2.10
33
April 24, 2006
HT49R50A-1/HT49C50-1/HT49C50L
RET Description Operation Affected flag(s) TO 3/4 RET A,x Description Operation PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Return from subroutine The program counter is restored from the stack. This is a 2-cycle instruction. Program Counter Stack
Return and place immediate data in the accumulator The program counter is restored from the stack and the accumulator loaded with the specified 8-bit immediate data. Program Counter Stack ACC x TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
RETI Description Operation
Return from interrupt The program counter is restored from the stack, and interrupts are enabled by setting the EMI bit. EMI is the enable master (global) interrupt bit. Program Counter Stack EMI 1 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
RL [m] Description Operation
Rotate data memory left The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0. [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 [m].7 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
RLA [m] Description Operation
Rotate data memory left and place result in the accumulator Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. ACC.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 [m].7 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
Rev. 2.10
34
April 24, 2006
HT49R50A-1/HT49C50-1/HT49C50L
RLC [m] Description Operation Rotate data memory left through carry The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit; the original carry flag is rotated into the bit 0 position. [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 C C [m].7 TO 3/4 RLCA [m] Description PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Affected flag(s)
Rotate left through carry and place result in the accumulator Data in the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored in the accumulator but the contents of the data memory remain unchanged. ACC.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 C C [m].7 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Operation
Affected flag(s)
RR [m] Description Operation
Rotate data memory right The contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7. [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 [m].0 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
RRA [m] Description Operation
Rotate right and place result in the accumulator Data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. ACC.(i) [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 [m].0 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
RRC [m] Description Operation
Rotate data memory right through carry The contents of the specified data memory and the carry flag are together rotated 1 bit right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 C C [m].0 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Affected flag(s)
Rev. 2.10
35
April 24, 2006
HT49R50A-1/HT49C50-1/HT49C50L
RRCA [m] Description Rotate right through carry and place result in the accumulator Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is stored in the accumulator. The contents of the data memory remain unchanged. ACC.i [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 C C [m].0 TO 3/4 SBC A,[m] Description Operation Affected flag(s) TO 3/4 SBCM A,[m] Description Operation Affected flag(s) TO 3/4 SDZ [m] Description PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Operation
Affected flag(s)
Subtract data memory and carry from the accumulator The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the accumulator. ACC ACC+[m]+C
Subtract data memory and carry from the accumulator The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the data memory. [m] ACC+[m]+C
Skip if decrement data memory is 0 The contents of the specified data memory are decremented by 1. If the result is 0, the next instruction is skipped. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]-1)=0, [m] ([m]-1) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
SDZA [m] Description
Decrement data memory and place result in ACC, skip if 0 The contents of the specified data memory are decremented by 1. If the result is 0, the next instruction is skipped. The result is stored in the accumulator but the data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]-1)=0, ACC ([m]-1) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
Rev. 2.10
36
April 24, 2006
HT49R50A-1/HT49C50-1/HT49C50L
SET [m] Description Operation Affected flag(s) TO 3/4 SET [m]. i Description Operation Affected flag(s) TO 3/4 SIZ [m] Description PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Set data memory Each pin of the specified data memory is set to 1. [m] FFH
Set bit of data memory Bit i of the specified data memory is set to 1. [m].i 1
Skip if increment data memory is 0 The contents of the specified data memory are incremented by 1. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]+1)=0, [m] ([m]+1) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
SIZA [m] Description
Increment data memory and place result in ACC, skip if 0 The contents of the specified data memory are incremented by 1. If the result is 0, the next instruction is skipped and the result is stored in the accumulator. The data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]+1)=0, ACC ([m]+1) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
SNZ [m].i Description
Skip if bit i of the data memory is not 0 If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data memory is not 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m].i0
Operation Affected flag(s)
TO 3/4
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Rev. 2.10
37
April 24, 2006
HT49R50A-1/HT49C50-1/HT49C50L
SUB A,[m] Description Operation Affected flag(s) TO 3/4 SUBM A,[m] Description Operation Affected flag(s) TO 3/4 SUB A,x Description Operation Affected flag(s) TO 3/4 SWAP [m] Description Operation Affected flag(s) TO 3/4 SWAPA [m] Description Operation PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O Subtract data memory from the accumulator The specified data memory is subtracted from the contents of the accumulator, leaving the result in the accumulator. ACC ACC+[m]+1
Subtract data memory from the accumulator The specified data memory is subtracted from the contents of the accumulator, leaving the result in the data memory. [m] ACC+[m]+1
Subtract immediate data from the accumulator The immediate data specified by the code is subtracted from the contents of the accumulator, leaving the result in the accumulator. ACC ACC+x+1
Swap nibbles within the data memory The low-order and high-order nibbles of the specified data memory (1 of the data memories) are interchanged. [m].3~[m].0 [m].7~[m].4
Swap data memory and place result in the accumulator The low-order and high-order nibbles of the specified data memory are interchanged, writing the result to the accumulator. The contents of the data memory remain unchanged. ACC.3~ACC.0 [m].7~[m].4 ACC.7~ACC.4 [m].3~[m].0 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
Rev. 2.10
38
April 24, 2006
HT49R50A-1/HT49C50-1/HT49C50L
SZ [m] Description Skip if data memory is 0 If the contents of the specified data memory are 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m]=0
Operation Affected flag(s)
TO 3/4 SZA [m] Description
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Move data memory to ACC, skip if 0 The contents of the specified data memory are copied to the accumulator. If the contents is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m]=0
Operation Affected flag(s)
TO 3/4 SZ [m].i Description
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Skip if bit i of the data memory is 0 If bit i of the specified data memory is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m].i=0
Operation Affected flag(s)
TO 3/4 TABRDC [m] Description Operation
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Move the ROM code (current page) to TBLH and data memory The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved to the specified data memory and the high byte transferred to TBLH directly. [m] ROM code (low byte) TBLH ROM code (high byte) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
TABRDL [m] Description Operation
Move the ROM code (last page) to TBLH and data memory The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to the data memory and the high byte transferred to TBLH directly. [m] ROM code (low byte) TBLH ROM code (high byte) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
Rev. 2.10
39
April 24, 2006
HT49R50A-1/HT49C50-1/HT49C50L
XOR A,[m] Description Operation Affected flag(s) TO 3/4 XORM A,[m] Description Operation Affected flag(s) TO 3/4 XOR A,x Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 Logical XOR accumulator with data memory Data in the accumulator and the indicated data memory perform a bitwise logical Exclusive_OR operation and the result is stored in the accumulator. ACC ACC XOR [m]
Logical XOR data memory with the accumulator Data in the indicated data memory and the accumulator perform a bitwise logical Exclusive_OR operation. The result is stored in the data memory. The 0 flag is affected. [m] ACC XOR [m]
Logical XOR immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR operation. The result is stored in the accumulator. The 0 flag is affected. ACC ACC XOR x
Rev. 2.10
40
April 24, 2006
HT49R50A-1/HT49C50-1/HT49C50L
Package Information
48-pin SSOP (300mil) Outline Dimensions
48 A
25 B
1 C C'
24
G H a F
D E
Symbol A B C C D E F G H a
Dimensions in mil Min. 395 291 8 613 85 3/4 4 25 4 0 Nom. 3/4 3/4 3/4 3/4 3/4 25 3/4 3/4 3/4 3/4 Max. 420 299 12 637 99 3/4 10 35 12 8
Rev. 2.10
41
April 24, 2006
HT49R50A-1/HT49C50-1/HT49C50L
100-pin QFP (1420) Outline Dimensions
C D 80 51 G H
I 81 50
F A B
E
100
31 K 1 30 a J
Symbol A B C D E F G H I J K a
Dimensions in mm Min. 18.50 13.90 24.50 19.90 3/4 3/4 2.50 3/4 3/4 1 0.10 0 Nom. 3/4 3/4 3/4 3/4 0.65 0.30 3/4 3/4 0.10 3/4 3/4 3/4 Max. 19.20 14.10 25.20 20.10 3/4 3/4 3.10 3.40 3/4 1.40 0.20 7
Rev. 2.10
42
April 24, 2006
HT49R50A-1/HT49C50-1/HT49C50L
Product Tape and Reel Specifications
Reel Dimensions
T2 D
A
B
C
T1
SSOP 48W Symbol A B C D T1 T2 Description Reel Outer Diameter Reel Inner Diameter Spindle Hole Diameter Key Slit Width Space Between Flange Reel Thickness Dimensions in mm 3301.0 1000.1 13.0+0.5 -0.2 2.00.5 32.2+0.3 -0.2 38.20.2
Rev. 2.10
43
April 24, 2006
HT49R50A-1/HT49C50-1/HT49C50L
Carrier Tape Dimensions
D
E F W C B0
P0
P1
t
D1
P K2 A0
K1
SSOP 48W Symbol W P E F D D1 P0 P1 A0 B0 K1 K2 t C Description Carrier Tape Width Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Cavity Depth Carrier Tape Thickness Cover Tape Width Dimensions in mm 32.00.3 16.00.1 1.750.1 14.20.1 2.0 Min. 1.5+0.25 4.00.1 2.00.1 12.00.1 16.200.1 2.40.1 3.20.1 0.350.05 25.5
Rev. 2.10
44
April 24, 2006
HT49R50A-1/HT49C50-1/HT49C50L
Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shanghai Sales Office) 7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233 Tel: 021-6485-5560 Fax: 021-6485-0313 http://www.holtek.com.cn Holtek Semiconductor Inc. (Shenzhen Sales Office) 43F, SEG Plaza, Shen Nan Zhong Road, Shenzhen, China 518031 Tel: 0755-8346-5589 Fax: 0755-8346-5590 ISDN: 0755-8346-5591 Holtek Semiconductor Inc. (Beijing Sales Office) Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031 Tel: 010-6641-0030, 6641-7751, 6641-7752 Fax: 010-6641-0125 Holmate Semiconductor, Inc. (North America Sales Office) 46712 Fremont Blvd., Fremont, CA 94538 Tel: 510-252-9880 Fax: 510-252-9885 http://www.holmate.com
Copyright O 2006 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holteks products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
Rev. 2.10
45
April 24, 2006

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